feng luo

Feng Luo has a total work experience of 13 years. They started their career as a Postgraduate on ASIC at the National ASIC System Engineering Research Center of SEU from September 2007 to April 2010. They then worked as an ASIC Design Engineer at Marvell Semiconductor from April 2010 to August 2013, where they were responsible for function verification in TD_LTE modem and took charge of TD/LTE macro synthesis/FV/CLP/STA in series of SOC chips. From August 2013 to April 2015, they worked as an Application Consultant at Synopsys Inc, where they resolved Front End(DC/PT/FM/DFT) tool's issues and provided design services to customers. Following this, they worked as a Senior Engineer at Beijing Pinecone Electronics Co. Ltd. from April 2015 to November 2015. Currently, Feng Luo is a Senior Principal Application Engineer at Cadence, starting from November 2015.

Feng Luo received a Master's degree in Circuit and System from Southeast University, where they studied from 2007 to 2010. Prior to that, they attended Xi'an University of Posts and Telecommunications, the details of which are unavailable.