Ajay M.

Ajay M. is an experienced Analog/RF Design Engineer currently working at Phoelex since June 2022. Prior to this, Ajay held a similar position at FermionIC Design from December 2020 to May 2022, where responsibilities included designing high-speed CTLE, TIA, CML drivers, RF matching, and power management blocks for PCIE5 SERDES. Ajay's career also includes a role as an Analog Characterization Engineer at Texas Instruments from July 2018 to December 2020, focusing on the validation and characterization of high-speed 5G transceivers, fractional PLLs, and RF matching networks. Ajay holds a Bachelor’s degree in Electrical Engineering from the Indian Institute of Technology, Madras, completed in 2018.