JL

Jeff Liu

Lead Modelling Engineer at PragmatIC Semiconductor

Jeff Liu is a Lead Modelling Engineer at Pragmatic Semiconductor, where responsibilities include defining and executing platform characterization plans and facilitating the transition of emerging technology from initial understanding to volume release. Prior experience includes roles as a Modelling Engineer and Graduate PDK Engineer at Pragmatic Semiconductor, where contributions involved refining a CMC compact SPICE model for unique TFT transistors, securing a pending US patent, devising characterization test plans, and supporting IC designers in circuit simulations. Additional experience as a Design Verification Engineer at MediaTek focused on IP analysis and functional verification for mmWave 5G RFIC. Jeff Liu holds a Master of Science in Microelectronics from Newcastle University and a Bachelor of Science in Electronic Engineering from National Kaohsiung University of Science and Technology.

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