Parul Agarwal

Parul Agarwal's work experience includes serving as a Digital Design and Integration Lead at PsiQuantum since 2021. Prior to that, they worked as a SoC Design Engineer at Intel Corporation from 2016 to 2021. Before joining Intel, Parul was a Design engineer III at Collabera Inc. from 2014 to 2016, where they worked on Qualcomm Design blocks and handled various digital design and implementation tasks. From 2011 to 2013, they worked as a Project Lead at Atrenta, leading the PV group for Gensys and establishing a successful product validation team. Additionally, Parul has experience as a Tech. Lead, Senior Design Engineer, and Design Engineer at STMicroelectronics Pvt Ltd from 2004 to 2011, working on front end design, specifications, synthesis, timing analysis, and bug analysis for digital IP's.

Parul Agarwal completed a Master's degree in Management Information Systems, General at Coleman College from 2014 to 2015. Parul earned a B. Tech. degree in Electronics & Communication from Mahatma Jyotiba Phule Rohilkhand University from 1999 to 2003. Additionally, they completed their 12th grade education, focusing on Science, Computers, and English, at Sacred Heart Convent Senior Secondary School, Mathura from 1996 to 1997. Parul also achieved their 10th grade education, studying Science, English, Hindi, and Computers, at St. Paul's School, Moradabad from 1994 to 1995.