Dharmesh Gurjar

Dharmesh Gurjar is a Senior Design Verification Engineer at Qualcomm, with over 3.5 years of experience in the Design and Verification domain. Previously, they worked as an ASIC Design Verification Engineer at eInfochips and held a position as a Design Engineer II at Cadence Design Systems. Dharmesh has a strong background in industry standard tools and technologies, focusing on UCIe controller IP and subsystem verification, as well as verification for PCIe and CXL 2.0. They hold a Bachelor’s degree in Electronics Engineering from The Maharaja Sayajirao University of Baroda, where they also contributed as the Training and Placement Cell Coordinator.