Lahari Puralachetty

Lahari Puralachetty is a skilled GPU Verification Engineer with extensive experience in block-level GPU design verification. Currently serving as a Staff Engineer at Qualcomm since 2018, Lahari works on verification of the High-Level Sequencer for shader processors and leads design verification for Low-Resolution Z filtering blocks. Prior to this role, Lahari was a Senior Design Engineer at Cadence Design Systems where they specialized in the functional verification of various PHY protocols and developed reusable verification environments. Lahari holds a Master's degree in VLSI from NIT Warangal and completed additional training in UVM and System Verilog.