Lekhya Sirivelu

Lekhya Sirivelu is a Staff Engineer at Qualcomm, specializing in RTL design for FPGA and ASIC projects using Verilog, UVM, and SystemVerilog. They previously worked as a Modem Design Verification Engineer at Intel Corporation from 2018 to 2019 and held the role of RTL Design Engineer-3 at Hughes Network Systems from 2014 to 2018. Lekhya began their career as an Engineer-I at Powerwave Technologies in 2011 and obtained a Master's degree in Electrical and Electronics Engineering from North Carolina State University in 2014.