Sreekanth Narayanan

Sreekanth Narayanan is a Senior Staff Engineer at Qualcomm, where they are involved in the development of RTL verification solutions and lead design verification activities for next-generation Snapdragon-based DDR subsystem designs. With over 14 years of industrial experience in pre-silicon verification, Sreekanth's previous roles include positions at Ampere, Applied Micro, and Intel, where they focused on cache coherency and memory subsystem design verification using UVM and SystemVerilog. Sreekanth earned a B.Tech in Electronics & Instrumentation from the College of Engineering and an M.Tech in VLSI from VIT University.