Yogesh Patil

Yogesh Patil is a Staff Engineer at Qualcomm, specializing in power estimation and modeling for DDRSS since 2022. Previously, at Intel Corporation from 2015 to 2018, they contributed to SRAM design and dynamic timing analysis across multiple generations of Intel processors. Yogesh also served as a Senior Design Engineer at Mirafra Technologies in 2019-2020, where they focused on low-power design and constraints integration at the SoC level. They earned a Master's degree in Electrical and Electronics Engineering from the Indian Institute of Technology, Bombay, in 2015.