Jean-François Bignolles

Jean-François Bignolles has over 20 years of experience in the field of engineering, specifically in the area of FPGA and ASIC design. Jean-François started their career as a software developer at i4i in 1998. From 2000 to 2007, they worked on validation and functional testing of ASICs and FPGAs, with projects involving companies such as Airbus Defence & Space and Texas Instruments. In 2008, they became an FPGA design engineer with various missions, including FPGA development, IP development, and software development related to hardware development. Jean-François has experience with simulation tools like ModelSim/QuestaSim and ActiveHDL, as well as design tools like Quartus, Xilinx ISE/Vivado, Libero, and Lattice Diamond. From 2016 to 2018, Jean-François worked as an FPGA design engineer at Médiante Système, where they were responsible for FPGA design, documentation writing, and validation for clients such as Cobham Avionics and Thales. Most recently, since 2018, they have been working as a Digital IC design engineer at SCALINX.

Jean-François Bignolles obtained a Bachelor's degree in Computer Science from UVSQ Université de Versailles Saint-Quentin-en-Yvelines, starting in 1994 and ending in 1996. Jean-François then pursued higher education at Pierre and Marie Curie University, where they completed a DEA degree in Micro-électronique from 1996 to 1997.