Daryl Kowalski

Daryl Kowalski is a seasoned engineer with extensive experience in ASIC design and development. Currently serving as a Senior ASIC Design Engineer at SEAKR Engineering, Inc. since August 2019, Daryl specializes in flow development for high-performance mil-aero signal processing ASIC chiplets, focusing on synthesis, floorplanning, DFT, and static timing analysis. Prior to this role, Daryl worked at Hewlett Packard Enterprise as a VLSI Design Engineer, leading the physical development of high-capacity ASICs for HPC systems. Daryl's career also includes positions at Real Intent, Avago Technologies, Cornice, Inc., and an earlier tenure at SEAKR Engineering, with expertise in technical marketing, power integrity analysis, and UVM design verification. Daryl holds a B.S. in Computer Engineering from the University of Illinois Urbana-Champaign and an MBA from Regis University.