Josh Laney

Joshua Laney is a Firmware Engineer at SEATREC, with prior experience as a Hardware Engineer at Viasat Inc., where Joshua worked on digital hardware and RTL design for a direct sampling radio for LEO satellites. Joshua has extensive experience in FPGA design, having completed an MSc individual research project at Imperial College London focused on high radix arithmetic for FPGA overclocking. Previous roles include an Electrical Engineering Intern at Carnegie Robotics LLC, where Joshua designed custom PCBAs and developed testing devices, and an Undergraduate Teaching Assistant at the University of Virginia, where Joshua supported students in computer architecture. Joshua holds a Master of Science in Electrical Engineering from Imperial College London and a Bachelor of Science in Electrical Engineering from the University of Virginia.