Latha

Latha BS is an experienced engineer specializing in Synthesis and Static Timing Analysis (STA) with a current position at SeviTech Systems Pvt. Ltd. since December 2020. Prior roles include serving as a Physical Design Engineer at Altran and Altan CalSoft Labs Private Limited from September 2018 to August 2020 and January 2017 to March 2018, respectively, as well as working on the APR flow at Neoschip Semiconductor in late 2016. Latha began a professional career as a Physical Design Trainee at Rv-VLSI Design Center in 2015 and interned as a tester at National Aerospace Laboratories from June 2014 to July 2015. Latha holds a Master’s Degree in VLSI Design and Embedded Systems from Vishveshwarya Technological University, attained between 2013 and 2015.