Joshua Smith

Joshua Smith is a highly experienced engineer specializing in micro-architecture and RTL design, currently serving as a Senior Principal RISC-V Core Designer at SiFive since April 2018. Joshua leads the design of SiFive's out-of-order RISC-V cores, including critical components such as instruction fetch, branch prediction, and scheduling units. Prior experience includes roles at Apple, where contributions were made to the development of high-performance ARM cores, and at Marvell Semiconductor, where Joshua worked on micro-architecture definition and RTL design for ARM processors. Joshua's career also includes positions at NVIDIA, ARM, and Cisco Systems, as well as academic experience as a Graduate Student Instructor at the University of Michigan, where Joshua earned both a BSE and an MSE in Computer Engineering.