Vithurson Subasharan is an experienced engineer specializing in RTL design, currently serving as Engineer II at SiFive since February 2022. Subasharan has a strong background in RISC-V core development through independent research and development activities since March 2017. Prior experience includes a role as a Research Engineer at SMU School of Information Systems from March 2020 to January 2022 and as a Research and Development Engineer at Synopsys Inc from February 2018 to February 2020, focusing on RTL development for FPGA acceleration. Vithurson Subasharan holds a Bachelor of Science with honors in Electronics and Telecommunications Engineering from the University of Moratuwa, completed in 2018.
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