Lavesh Jain

Lavesh Jain is a skilled Digital Design Engineer with a focus on design and verification in the semiconductor industry. Currently, Lavesh holds the position of Digital Design Engineer-II at SignOff Semiconductors since July 2021, specializing in RTL design, RTL integration, linting, and synthesis, utilizing tools such as UVM, SV, VERILOG, and ARM technologies. Previously, Lavesh worked as Digital Design Engineer-I at Maven Silicon and completed a research internship at the Indian Institute of Technology, Patna. Lavesh holds a Master of Technology in Microelectronic and VLSI design from Shri G S Institute of Technology & Science and a Bachelor of Engineering in Electronics and Communications Engineering from Rajiv Gandhi Prodyogiki Vishwavidyalaya.