Praveen Naddi

Praveen Naddi is a highly experienced professional in the field of CAD and EDA methodologies, currently serving as Lead CAD FE DV Infrastructure at Silicon Labs since April 2024. In this role, Praveen oversees SOC and ASIC Front-End design, focusing on EDA tool development and collaboration across multiple global design centers. Prior to Silicon Labs, Praveen worked as a Senior CAD/EDA Methodology Verification Engineer at Intel Corporation, where responsibilities included optimizing simulation environments and supporting test list conversion. Earlier experience includes roles at SignOff Semiconductors, Arm, and Skandysys, where Praveen contributed to design verification and testing. Praveen holds an MTech in Digital Electronics & Communication Systems and a BTech in Electronics and Communication Engineering from Jawaharlal Nehru Technological University.