Praveen Naddi

Praveen Naddi is a seasoned engineering professional with extensive experience in CAD verification and design verification across multiple prestigious organizations in the semiconductor industry. Currently serving as the Lead CAD Verification Engineer at Silicon Labs since April 2024, Praveen previously held the position of Senior CAD/EDA Methodology Verification Engineer at Intel Corporation from September 2021 to April 2024. Additional experience includes roles as a Design Verification Engineer 2 at SignOff Semiconductors, a Verification Engineer 1 at Arm, and a Design Verification Engineer at Skandysys, part of Marvell. Praveen's educational background includes an MTech in Digital Electronics & Communication Systems and a BTech in Electronics and Communication Engineering, both from Jawaharlal Nehru Technological University.