Sumit Jain

Sumit Jain has been working in the field of Design Verification since 2011. In 2011, they completed a HEP training on Verification of Electronics Design and Systems using System Verilog at Mentor Graphics. Sumit then joined Masamb Electronics Systems as a Design Verification Engineer, where they were responsible for understanding design with the help of specification and creating the verification plan. Sumit also prepared the verification platform for the testing of the IP in UVM and implemented checker module by using System Verilog Assertions (SVA). In 2014, they joined CVC Pvt Ltd as an ASIC DV Consultant, where they worked as a verification consultant and was involved in the verification of AHB-Lite protocol, Ethernet Parser & Router, and Basic and Modified Memory model by using SV Layered Verification Environment. Sumit also completed a 3-week training on "Verification using System Verilog and UVM Methodology". In the same year, they joined MediaTek as a Senior Engineer, where they were completely involved in the verification of Interrupt request controller (CIRQ) IP (modem sub-system). In 2018, they joined Western Digital as a Staff Engineer, where they were responsible for the verification of Clock/Reset IP (CMC), Debugger IP (ATB) and Test/Debug IP (Test mode controller) at NAND Controller SOC. In 2020, they joined Intel Corporation as a DV Engineer, where they created SOC infra test bench from scratch and enabled all the SOC models and common TB flows. Currently, they are employed at SiMa.ai as a DV Engineer.

Sumit Jain completed their Bachelor of Technology (B.Tech.) in Electronics and Communications Engineering from Kautilya Institute of Technology and Engineering, Jaipur between 2007 and 2011.