Massimiliano Capacchione

Massimiliano Capacchione is a Project Engineer at SITTI since March 2024, previously serving as a Senior Network Design Engineer at SIAE Microelettronica from December 2009 to March 2024. Expertise includes network planning with experience in link design, service provisioning, Layer 3 routing protocols, and scripting for equipment configuration. Capacchione has a strong background in network maintenance and monitoring, software development involving AI-ML algorithms, and technical consultancy. Earlier experience includes a role as a researcher at Politecnico di Milano focused on smart antennas for MIMO applications. Massimiliano Capacchione holds a Master's degree and a Bachelor's degree in Telecommunications Engineering from Politecnico di Milano, completed in 2008 and 2006, respectively.