Cheng Guo

Cheng Guo has work experience as a Senior Firmware Engineer at SK hynix memory solutions inc. from August 2018 to the present. In this role, they have prototyped Xtensa and TIE based Firmware capable of communicating with other hardware accelerators to achieve high-performance eSSD controller design architecture. Cheng has also validated functionality through DV test cases and FPGA validation FW, as well as developed different versions of C code for DV, FPGA validation, Veloce validation, and chip bringup.

Prior to their current role, Cheng Guo had an internship as an MCU Designer at Sino Wealth Electronic(Shanghai) Ltd. from May 2016 to October 2016. Cheng also had an internship as a Hardware Designer at Shanghai Basewin Technology Co.,Ltd. from May 2014 to October 2014.

Cheng Guo completed a Bachelor of Engineering (BE) degree in Electrical and Computer Engineering from the University of Connecticut from 2012 to 2016. Later, Cheng obtained a Master of Engineering (MEng) degree in Electrical Engineering with a focus on Circuit & Embedded System Track from UCLA from 2016 to 2017.