Jinliang Mao [Gold Mao]

Jinliang Mao, also known as Gold Mao, has a strong background in ASIC engineering and extensive experience in the semiconductor industry. Jinliang started their career at VIA Technologies, Inc. in 2002 as an ASIC Engineer, where they worked on projects involving North Bridge verification and Production Test, as well as PCI Express PHY verification and PMU. In 2004, Mao took on a Senior ASIC Engineer role at VIA Technologies and continued to work on various projects, such as PCIE-I Root, PCIE-II Root, and Hyper Transport 3.0. In 2010, they joined VIA Telecom as a Senior ASIC Engineer before moving to Marvell Semiconductor in 2012. At Marvell Semiconductor, Mao held multiple roles, including Senior Engineer, Staff ASIC Engineer, and Senior Staff Engineer, where they worked on projects related to DDR interface verification, SOC integration and verification, and serving as a technical lead for next version PCIE-SSD SOC. Mao is currently working at SK hynix memory solutions America Inc. since 2015, where they hold the position of Principal Engineer and is responsible for leading and overseeing engineering projects.

Jinliang Mao, also known as Gold Mao, pursued their education at Tsinghua University, where they obtained a Bachelor of Science degree in Electronics Engineering with a specialization in Microelectronics. This educational journey lasted from 1994 to 1999. Subsequently, Mao continued their studies at Tsinghua University, completing a Master of Science degree in VLSI Design from 1999 to 2002.