Venkata Kandala

Venkata Kandala has a diverse work experience spanning over a decade in the field of ASIC engineering and design verification. Starting in 2008, they worked as an ASIC Design and Verification Engineer at Tata Consultancy Services Ltd, where they primarily focused on the verification of GMAC with Descriptor based DMA using OVM and System Verilog. Venkata'sresponsibilities included creating a verification plan using Transaction level modeling and developing test benches, drivers, monitors, and coverage collectors.

In 2012, Venkata joined Qualcomm as a Design Verification Engineer, where they worked on the design verification of Power Management Integrated Circuits (PMIC). Venkata developed a generic reusable TB architecture, documented the verification plan, and created test bench scripts and verification reports. Venkata also played a key role in the verification environment development using UVM Methodology and was responsible for the test plan, environment plan, and test case creation.

From 2013 to 2017, Venkata worked at Juniper Networks as an ASIC Engineer. Venkata'sresponsibilities included working on packet processing and filter blocks, as well as virtual router modeling. Venkata gained experience in these areas while also contributing to other aspects of ASIC engineering.

Most recently, in 2018, Venkata joined SK hynix memory solutions America Inc. as an ASIC Engineer. Although the specific details of their role are not provided, this position showcases their continued expertise and growth in the field of ASIC engineering.

Throughout their career, Venkata has consistently demonstrated their skills in ASIC engineering, design verification, and system-level modeling.

Venkata Kandala completed a Master of Engineering degree in Microelectronics from the Rochester Institute of Technology in 2010-2011. Prior to this, they attended PSG College of Technology, where they focused on VLSI design. No specific degree was specified for their studies at PSG College of Technology.