Meghna Agrawal

Meghna Agrawal has a long and varied work experience. Meghna began their career in 2005 as a Lead Design Engineer at Conexant Systems Inc, where they developed several DSP baseband algorithms and implemented them in C for MoCA, Gigabit Ethernet and WiFi-802.11n. In 2008, they moved to Atheros Communication as a Lead Senior Engineer, where they designed and implemented Rate Control and Aggregation Algorithm for video streams to provide reliable throughput. In 2012, they joined Qualcomm as a Staff Engineer, where they designed algorithms for mobile and server applications, prototyped and verified them using Matlab/python, and analyzed crowd-sourced data to determine current system limitations and develop new features. In 2018, they moved to Intel Corporation as a SW Architect. Finally, in 2019, they joined Skylo Technologies as the Director of Algorithms Engineering.

Meghna Agrawal completed a Bachelor of Engineering (BE) in Electronics and Communications Engineering from M.B.M. Engineering College, Jodhpur in 2003. Meghna then pursued a Master of Engineering (MEng) in Telecommunication at the Indian Institute of Science (IISc) and graduated in 2005.