Padma Vasanthi Kappaganthula

Design Verification Engineer at SmartSoC Solutions Pvt Ltd

Padma Vasanthi Kappaganthula currently serves as a Design Engineer I at Wafer Space - An ACL Digital Company, starting in July 2024. Prior to this role, Padma Vasanthi worked as a Design Engineer I at HySoC Technologies Pvt Ltd from September 2021 to July 2024. Additionally, a position as a Design Verification Trainee was held at Maven Silicon from July 2023 to December 2023, and experience was gained as a Contingent Worker at AMD from September 2021 to November 2023. Academic qualifications include a Bachelor of Technology in Computer Science from MVR College of Engineering & Technology, obtained from June 2017 to July 2021.

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