Shabbir Saifee

Shabbir Saifee is a seasoned engineering professional with extensive experience in micro-architecture and design engineering. Currently serving as a Senior Design Engineer at Intel Corporation since September 2016, Shabbir leads initiatives to enhance virtualization IP performance and subsystem architecture while fostering team expertise in coherency and security. Prior to this role, Shabbir took on design engineering positions at Soft Machines, where DDRx IP was micro-architected and RTL coded from scratch, and at Xilinx, focusing on MC-PHY interface updates and automation for DDR PHY characterization. Earlier experience includes work as an ASIC Engineer at eInfochips, where various VIP implementations and FPGA solutions were developed, and a project trainee position at Space Applications Centre, ISRO, working on a Viterbi Decoder IP for space communications. Shabbir holds a degree from Visvesvaraya Technological University.