Parul Raj is an experienced engineering professional with expertise in ASIC and FPGA verification, currently serving as the ASIC Verification Team Lead at SpaceX since November 2022. Prior to this role, Parul worked at Apple as a Design Verification Engineer from July 2019 to November 2022 and held various positions at NYU Tandon School of Engineering, including Graduate Teaching Assistant and Undergraduate Teaching Assistant. Parul also gained industry experience as an Intern Technical Engineer at Synopsys Inc in 2018 and as an R&D Engineer 2 at Synopsys Inc from June 2014 to July 2017. Parul holds a Master's degree in Computer Engineering from New York University and a Bachelor's degree in Electronics and Communications Engineering from Netaji Subhas Institute of Technology.
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