MM

Milos Marinkovic

Senior VLSI Design Engineer at Speedata.io

Milos Marinkovic has extensive work experience in VLSI design engineering. Milos is currently working as a Senior VLSI Design Engineer at Speedata.io since March 2022. Before that, they worked at Veriest as a Senior Design Engineer from May 2020 to February 2022. Milos also had multiple roles at Veriest, including Design Verification Engineer and Contractor on CEVA CNN Project. Prior to that, they worked as a Senior Design Verification Engineer at HDL Design House from February 2014 to July 2014. Milos also worked at ELSYS Eastern Europe as a Senior Digital Design Engineer and Senior Digital Design/Verification Engineer from September 2011 to December 2013. Before that, they worked at Forma Ideale as a Maintenance Manager from July 2007 to September 2011 and as a Maintenance Engineer from March 2007 to July 2007. Milos'searlier experience includes working at HDL Design House as an ASIC Verification Engineer, VHDL/Verilog behavioral modeling and verification engineer, and ASIC Design Engineer from August 2002 to March 2007. In their roles, they have worked on various projects and performed tasks such as design, verification, and maintenance of modules, coordination with team members, training preparation, and documentation development. Milos is skilled in using tools such as Synopsis Design Compiler, LEC, and Fastscan for synthesis.

Milos Marinkovic began their education in 1992 at Prva kragujevačka gimnazija, where they pursued a degree in Computer Programming with a focus on Mathematics. Milos completed their studies in 1996. In 1994 and 1995, Milos also attended Petnica, where they specialized in Parallel Computing, although they did not receive a specific degree from this institution. Following this, they attended the University of Belgrade from 1996 to 2002, where they obtained a Master of Science in Electrical Engineering with a concentration in Electronics and Semiconductors. In 2004, Milos attended the Reserve Officers Training Corps, where they received the rank of Second Lieutenant in Technical Support & Logistics.

Links


Org chart