Anjali Tailor

Anjali Tailor is a Senior Staff Engineer at STMicroelectronics, where they focus on advanced ATPG methodologies and DRC violation resolution. They previously held positions as a SoC Design Engineer at Intel Corporation and as a DFT Engineer at eInfochips, along with experience as a Technical Staff Member at Graphene Semiconductor Services. Anjali developed expertise in multiple testing modes and has conducted seminars on test compression architecture and X-masking techniques. Their education and training include a foundational role as an ASIC Trainee Engineer at eiTRA.