Bindiya Rajpal

Bindiya Rajpal is a Technical Lead at STMicroelectronics, specializing in Analog and Mixed-Signal Design within the Imaging R&D Group. They previously held positions as a Senior Analog Design Engineer and Analog Design Engineer at STMicroelectronics and 3rdiTech Inc., respectively. Bindiya's earlier experience includes serving as a Project Fellow at CSIR-CEERI, where they designed a novel CMOS capacitance to digital conversion circuit. They earned an M.Tech in VLSI Design from Banasthali Vidyapith and a B.E. in Electronics and Communications Engineering from RGPV Bhopal.