KAIS CHIBANI

Kais Chibani holds a PhD in Nanoelectronics and Nanotechnologies from Université Grenoble Alpes, where they also completed their doctoral research focused on enhancing the robustness of digital systems against security threats. They have served as a Sr. R&D Microelectronic Engineer at EASii IC and currently work as a Sr. Design Verification Engineer at STMicroelectronics. Earlier roles included positions as a Hardware Security Engineer at Secure-IC and a part-time lecturer at Grenoble INP. Kais possesses extensive expertise in ASIC design, cryptography, and verification environments, contributing to innovative security solutions throughout their career.