Palas Parmar

Palas Parmar is a Staff Engineer at STMicroelectronics, specializing in Synthesis and Static Timing Analysis with over eight years of experience in ASIC design. Currently responsible for DFT modes for automotive projects, Palas ensures timing analysis and signoff timing closure while mentoring colleagues in timing strategies. Previously, Palas held roles as a Lead Engineer and Senior Engineer, focusing on block-level synthesis and timing analysis at various leading tech companies. Palas earned a Master’s Degree in VLSI and Embedded Systems from the Dhirubhai Ambani Institute of Information and Communication Technology.