Pierpaolo Bernini is currently an Industrial Engineer at STMicroelectronics since January 2025. Prior experience includes serving as a Materials Planner at OFFICINE VICA S.p.A. from November 2021 to August 2025 and a Junior SAP Consultant at Syscons, where engagement involved a client project with Ferrero S.p.A. Educational background includes a Laurea Magistrale in Ingegneria gestionale/Gestione industriale from Politecnico di Torino (2017-2020), a laurea triennale in the same field from the same institution (2012-2017), and a Diploma from Liceo Scientifico PNI "Quintino Cataudella" (2007-2012).
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