Subramanian T R

Subramanian T R is a Senior Staff Design Engineer at Steradian Semiconductors, with expertise in continuous time Delta Sigma ADCs and Ethernet receiver design, including jitter budgeting and digital clock data recovery. Prior experience includes roles as Principal Design Engineer and Lead Design Engineer at Cadence Design Systems, focusing on multiphase injection locked ring oscillators and high-speed SERDES components, along with earlier positions as a Design Engineer and Research Assistant, working on low power receivers and digital phase locked loops. Subramanian holds a Master’s Degree in Electronics Design and Technology from the Indian Institute of Science and has completed significant academic research at Oregon State University and a Bachelor's Degree in Applied Electronics & Instrumentation from the College of Engineering Trivandrum.