Synapse Design Inc.
- Jiayou Wei
Jiayou Wei
Design Verification Engineer at Synapse Design Inc.
Jiayou Wei is a Design Verification Engineer at Synapse Design Inc. with previous experience as an FPGA Design Engineer at Marvell Technology. Jiayou Wei also served as a Graduate Student at the University of Michigan, focusing on VLSI and working as a Research Assistant in the same field.
Timeline
Design Verification Engineer
September, 2021 - present
Related people
Ayman Daraghmah
Design Verification Engineer at Ferroelectric Memory Company
Harshavardhan Reddy
Design Verification Engineer at ScaleFlux
Abdullah Tartir
Design Verification Engineer at Speedata.io
Bogdan Petrescu
Design Verification Engineer at NeuroBlade
Dharani Kumar Thumma
Design Verification Engineer at INVECAS