Achanta Hari is a skilled RTL Design Engineer with a background in Electronics and Communication, holding a Bachelor of Technology from V R Siddhartha. They achieved a ranking of AIR 410 in the GATE ECE examination. Currently, they serve as a Staff Engineer in ASIC Digital Design at Synopsys Inc. Previously, Achanta has worked as a Senior Engineer at eInfochips, an FPGA Design & RTL Application Engineer at Unistring Tech Solutions Pvt. Ltd., and a Senior Professional Engineer at Capgemini Engineering.
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