Adharsh S

Adharsh S is a Senior R&D Engineer at Synopsys, bringing expertise in the VLSI industry with strong skills in VHDL, Verilog, RTL coding, Universal Verification Methodology (UVM), and SystemVerilog. Adharsh previously served as a Sr. RTL Design Engineer at VVDN Technologies from 2019 to 2022 and worked as an R&D Engineer II at Synopsys. They graduated with a Bachelor of Technology in Electronics and Communications Engineering from Vidya Academy of Science and Technology and also completed advanced studies in VLSI design and verification at Maven Silicon.