Aditya Jha is an ASIC Digital Design Staff Engineer at Synopsys Inc, where they are currently applying their expertise in digital design. Aditya previously held positions as a Lead Design Engineer at Cadence Design Systems and worked at eInfochips, where they advanced from Engineer to Senior Engineer. With a Bachelor of Technology in Electronics and Communications Engineering from Kurukshetra University, Aditya has a strong background in RTL design, FPGA, and ASIC design flow, alongside proficiency in various programming and scripting languages.
This person is not in the org chart
This person is not in any teams
This person is not in any offices