Aditya Ranjan

Aditya Ranjan is an experienced ASIC Digital Design Engineer II at Synopsys Inc, having joined in December 2023. Prior to this role, Aditya worked as a Product Validation Engineer at Cadence Design Systems from May 2021 to December 2023, focusing on FPGA prototyping and developing synthesizable RTL designs. Aditya contributed to the development of a RISC-V microprocessor at the Indian Institute of Technology, Patna, and participated in research on memory models as an intern at the Indian Institute of Technology, Bombay. Aditya has also been active in circuit design and programming in robotics competitions and completed a summer internship at the Indian Institute of Technology Gandhinagar, analyzing memory performance using architectural simulators. Aditya holds a B.Tech degree in Electrical and Electronics Engineering from the Indian Institute of Technology, Patna, completed in 2021.