Adwait Purandare is an experienced ASIC Digital Design Engineer SR1 at Synopsys Inc, specializing in front end verification for high-speed SERDES chips since June 2019. Prior to this role, Adwait served as an Application Engineer and Associate Application Engineer at Mentor Graphics, focusing on the Questa Verification IP Suite and its deployment for customers in the Bay Area. Adwait’s expertise includes various protocols such as PCIe, DDRx, and Ethernet. Additionally, Adwait completed a Front End Design Internship at Microchip Technology and a Mixed Signal Design Internship at Analog Rails, contributing to scripting support and digital standard cell design, respectively. Adwait holds a Master of Science in Electrical Engineering from Arizona State University and a Bachelor of Engineering in Electrical, Electronics, and Communications Engineering from Pune Institute of Computer Technology.
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