Amit Tyagi

Amit Tyagi is a seasoned professional in R&D Engineering, currently serving as a Sr. Manager at Synopsys Inc, where they specialize in the development and deployment of Verification IPs. With a strong background in project planning, design, functional verification, and debugging using System Verilog, they possess expertise in various protocols including ONFI and AXI. Amit's career spans multiple roles at Synopsys, as well as positions at nSys Design Systems and Tech Mahindra. They hold a PG Diploma in VLSI Design from CDAC ACTS and a Bachelor's Degree in Electronics and Communications Engineering from GNIT.