Anand Agarwal

Anand Agarwal is a Staff Engineer at Synopsys, specializing in logic synthesis with expertise in hardware description languages including VHDL, Verilog, and SystemVerilog. Previously, Anand served as a Lecturer at TMU Moradabad and held various roles in tech companies, including Member of Technical Staff at Calypto Design Systems and Sr. Software Engineer at Atrenta. Anand completed a Master of Technology in Computer Science and Engineering at the Indian Institute of Technology, Delhi, following an M.C.A. in Computer Science from Nagpur University and a B.B.A. in Management from IMS Ghaziabad.