Anand Parameswaran

Anand Parameswaran is an experienced Staff R&D Engineer at Synopsys Inc since June 2014, where responsibilities include leading a team to verify DRAM PHY training algorithms for DDR4/DDR5 UDIMM/RDIMM/LRDIMM across multiple product lines. Prior experience includes serving as a Senior R&D Engineer involved in RTL design for DRAM PHY IP at Synopsys Inc, and holding various positions at Sonics Inc from August 2007 to May 2014, including Senior Logic Design Engineer, where Anand designed a router-based configurable Network-On-Chip fabric interconnect, and Logic Design Engineer, focusing on RTL microarchitecting. Anand began a career in design verification at AMD in early 2007 as an intern, focusing on power management verification. Educational qualifications include a Master's degree in Electrical Engineering (VLSI) from the University of Southern California and a Bachelor's degree in Engineering (Electrical) from the University of Mumbai.