Anannya Chatterjee

Anannya Chatterjee is a Senior Engineer in R&D Engineering at Synopsys, specializing in EDA tool development with a focus on DFT. With over three years of experience, they have developed expertise in DFT architecture and validation processes, actively contributing to the enhancement of Synopsys DFT tools. Previously, Anannya interned in layout design at STMicroelectronics, where they worked on analog cell layouts and performed essential design checks. They hold a Master’s degree in VLSI and Embedded Systems from IIIT Delhi and a Bachelor’s degree in Electronics and Communication from B.P. Poddar Institute of Management and Technology.