Andrea Ghilioni is a Senior Staff Engineer at Synopsys, specializing in system architecture for Ethernet and PCIe SerDes PHY. They possess extensive experience in the design and production of full custom ICs for advanced serial data communications, including design for both wireline and electro-optical technologies. Previously, Andrea served as an Assistant Professor at Università di Pavia, leading projects in advanced electro-optical transceiver development and contributing to academic courses in RF microelectronics. Their career includes roles at eSilicon, Inphi Corporation, and Marvell Technology, where they focused on DSP-based architectures and simulation frameworks for data links. Andrea earned a PhD in Microelectronics from Università di Pavia.
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