Andrea Mereu

Andrea Mereu is a Senior Staff Digital Design Engineer at Synopsys Inc, where employment commenced in January 2022, following previous roles as Staff Digital Design Engineer and Senior Digital Design Engineer. Prior experience includes serving as a Senior Digital Design Engineer and Digital Design Engineer at Qualcomm from March 2018 to December 2021, where contributions involved designing Clock Controller and Reset Generator IPs for Premium-Tier Snapdragon chipsets and developing Python scripts for automating Verilog RTL code. Additionally, Andrea conducted research at ISMB, focusing on a MATLAB model for SPR-based sensor performance related to water quality monitoring. Academic qualifications include a Master’s Degree in Electronic Engineering from Politecnico di Torino and a Bachelor’s Degree in Electronic Engineering from Università degli Studi di Cagliari.