Anees T I

Anees T I is a skilled Senior Analog Layout Engineer at SmartSoC Solutions Pvt Ltd, with extensive experience in the field of analog layouts. Previous positions include Analog Layout Engineer at Juntran Technologies Pvt Ltd and Analog Layout Design Engineer at Altran, demonstrating a progression of expertise in the industry since 2017. Proficient in using Cadence Virtuoso for various technology nodes including 28nm, 16nm, 7nm, and 5nm, Anees has successfully supported a range of blocks such as LDO, PLL, DLL, ESD, OpAmp, Level Shifter, Power Switch, and Counter. Academic credentials include a Bachelor of Technology in Electrical, Electronics and Communications Engineering from Ilahia College of Engineering and Technology, completed in 2015.