Ann Cheriyan

Ann Cheriyan is a Tech Lead at Synopsys Inc, bringing over nine years of experience in analog and mixed signal layout design, specializing in advanced technologies such as TSMC 5 nm and Intel 14 nm FINFET. Prior to their role at Synopsys, they worked as a Senior Analog Layout Design Engineer at Intel Corporation from 2010 to 2016 and as a Member of Technical Staff at Mirafra Technologies from 2016 to 2017. Ann earned a Bachelor's Degree in Electronics and Communications Engineering from LBS Centre for Science and Technology and a Master's Degree in Microelectronics with Distinction from Manipal University. They completed their high school education at Savio HSS Devagiri and St. Sebastian's H.S.S. Koodaranji.