Anuj Goyal is a seasoned professional in the field of electronics and communications engineering, currently serving as a Senior R&D Engineer at Synopsys Inc since July 2021, focusing on FPGA RAM Mapping and DSP Mapping projects. Previously, Anuj held various R&D engineering roles at Synopsys, contributing to the development of Synopsys Protocompiler and Synplify products. Anuj's earlier experience includes a technical traineeship at Nagarro, where skills in full-stack Java development were honed, and a mentorship role at StudentCode-in, promoting open-source initiatives. Additional experience encompasses a summer internship at the Indian Institute of Technology, Bombay, where a chemical simulator software was developed, along with participation as a beta tester for Udacity's Nanodegree Programs and involvement in the GirlScript Foundation's summer coding contest. Anuj holds a Bachelor of Technology degree in Electronics and Communications Engineering from Chandigarh College of Engineering & Technology, Panjab University, completed in 2021.
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