Anuj Kumar

Anuj Kumar is a highly experienced professional in the field of engineering, currently serving as Sr. Director of R&D Engineering and previously as Principal Engineer at Synopsys Inc since March 2011. Kumar has a strong background in timing analysis and extraction, leading teams in these areas. Prior experience includes a role as a Hardware Engineer at Cisco, where architectural specifications for MAC Security IP and significant contributions to 100G Port ASIC modules were made. Kumar also served as a Graduate Research Assistant at the University of Wisconsin-Madison, focusing on VLSI Design Automation Algorithms while assisting in teaching. Previous experiences include roles at Cadence Design Systems, STMicroelectronics Pvt Ltd, and Global Groupware Solutions, showcasing a diverse skill set in EDA tool development and behavioral synthesis. Anuj Kumar holds a Master’s degree in Electrical and Computer Engineering from the University of Wisconsin-Madison.