Arsen Asatryan

Arsen Asatryan is currently an R&D Engineer, Sr II at Synopsys, where responsibilities include exploring and developing logic library architecture in finFET technology and leading team projects with final QA verification. Previously, Arsen held roles as a Physical Design Engineer at Virage Logic, where they created and developed logic libraries across multiple technologies, and as a Shift Engineer at Intergovernmental TV & Radio Company MIR, ensuring connections between satellite stations. Arsen also gained foundational experience as an R&D Engineer at Yerevan Computer Research and Development Institute, focusing on electrical design and programming. Arsen earned both a Bachelor's and Master's degree from the State Engineering University of Armenia in the fields of Radio-Communications and Means of Communication.